1. Field of the Invention
The present invention relates to an image processing apparatus for performing three-dimensional (3-D) computer graphics (CG).
2. Description of the Related Art
Recently, game machines using computer graphics (CG) have become widely prevalent. Most of them are two-dimensional (2-D) CG systems. However, images produced by CG systems are generally short of naturalness. In order to overcome this drawback, a natural image is prepared as texture data, and a model image is subjected to a texture mapping process.
A conventional inexpensive CG system has a structure as shown in FIG. 1. Specifically, a graphics chip 100 is connected to a single address line 101 and a data line 102. The address line 101 and data line 102 are connected to first and second image memories 103 and 104. Each of the image memories 103 and 104 comprises a texture data area and a pixel data area. A model produced by pixel data is painted out by texture data by the following process. At first, the graphics chip 100 fetches polygon data from an external bus 105 and then texture data from the image memory 103. The graphics chip 100 executes graphics processing and writes the processing result (pixel data) in the image memory 103. Alternatively, texture data in the image memory 104 may be fetched to subject the pixel data in the image memory 103 to map processing.
In the above-described conventional CG system, the graphics chip 100 does not perform the fetching of texture data operation and the pixel data and writing in the image memory operation in parallel. Instead, the operations are performed serially, and a long processing time is required. This problem results from common use of the address line and data line in two memory banks (image memories 103 and 104).
The reason why the address line and data line are shared by the image memories 103 and 104 is that the number of pins can be decreased and the manufacturing cost decreased. Besides, since the conventional graphics chip 100 does not include a CRT controller, it is necessary to read out data from the image memory 103 or 104 and output the data to the external bus 105. When the internal memory of the graphics chips 100 is used to output data to the external bus 105, system control is made easier by sharing the address line and data line for the image memories 103 and 104. In the conventional system, in order to simplify the mapping algorithm, texture data is stored in a two-dimensional fashion. As a result, when multiport DRAMs are used as image memories 103 and 104 and are accessed, a considerable page break may frequently occur. Thus, the speed of the processing for subjecting polygons to texture mapping is much lower than that of the processing for drawing only polygons. Moreover, although the multiport DRAMs are used as image memories 103 and 104 in the conventional system, a refresh time period for refreshing a desired row address is set independently. Thus, the access to the DRAM is prohibited in the refresh time period, and the entire processing speed decreases further.
In order to solve the above problems, there is known a method of providing a texture cache memory within a system or within a graphics chip and making use of it as a data buffer. However, in a video game machine whose system is inexpensive, an increase in cost due to provision of a cache memory is a problem. Furthermore, even if a cache memory is provided, because original data is two-dimensional, a considerable degree of page break occurs when texture data is fetched in the cache memory. Consequently, the processing speed lowers.
As has been described above, in the conventional 3-D computer graphics, when texture mapping is performed on polygons, the processing speed lowers and high-speed plotting cannot be achieved. Furthermore, the manufacturing cost increases due to provision of a texture cache memory.